Troy a Tree Oriented Approach to Logic Synthesis and Technology Mapping
نویسندگان
چکیده
The problem of provable optimal synthesis of boolean functions for a given technology is still unsolved. In this paper we present a new approach to the synthesis of combinational circuits and the mapping of standard cells with arbitrary number of inputs. Our method is based on the provable optimal synthesis of the fanoutfree regions of a circuit, represented as Normal AND OR Trees. This representation enables TROY to rebalance the regions with respect to delay without sacrifying area and result in a larger search space than that used by Tree Matching. Fast heuristics derived from the optimal approach yield signiicantly better results than SIS on many standard benchmark circuits.
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